ASIC Design Verification Engineer

This is a fully remote position, open to applicants in United States.

📋 Description

• Create and implement verification strategies for block-level, subsystem-level, and full-chip environments.

• Develop SystemVerilog/UVM test benches, encompassing agents, monitors, scoreboards, checkers, and coverage models.

• Write SystemVerilog Assertions (SVA) and incorporate formal verification as necessary.

• Execute constrained-random and directed testing approaches to validate functionality, edge cases, and stress scenarios.

• Conduct simulations, analyze failures, perform root-cause investigations, and collaborate with RTL designers to address issues.

• Establish and sustain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.

• Oversee regression testing, simulation farms, and CI pipelines to guarantee high test throughput and rapid debug cycles.

• Engage in design reviews and discussions regarding microarchitecture.

⛳️ Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

• Over 3 years of experience in ASIC/SoC verification.

• Strong knowledge of SystemVerilog, digital logic, and hardware verification processes.

• Expertise with simulation tools (VCS, Xcelium, Questa), waveform debugging tools (Verdi, SimVision), and coverage tools.

• Experience in test planning, testbench development, constrained-random testing, and coverage analysis.

• Familiarity with a scripting language (e.g., Python, Perl, TCL) and version control systems (e.g., Git).

🏝️ Benefits

• Comprehensive benefits package including paid time off.

• Medical, dental, and vision coverage.

• Life insurance.

• Paid parental leave.

• Numerous other perks.