This is a fully remote position, open to applicants in Arizona.

📋 Description

• Validate ASIC/FPGA designs using testing and simulation techniques.

• Create comprehensive test and simulation strategies.

• Design UVM testbenches for effective verification.

• Assess results and evaluate performance metrics.

• Assist in defining architecture and module interfaces.

⛳️ Requirements

• A Bachelor's degree in Electrical or Computer Engineering or a related STEM discipline, along with 5+ years of relevant experience, or a Master's degree with 3 years of experience.

• U.S. citizenship is a prerequisite for this position.

• Preferred: Experience with RTL simulation using Questa or ModelSim on Linux.

• Preferred: Proficiency in SystemVerilog OOP and UVM, encompassing testbench architecture, agents, bus functional models, RAL, functional coverage, assertions, and constrained random.

• Preferred: Familiarity with requirements-based verification and formal verification tools.

• Preferred: Scripting skills in shell, Tcl, or Python.

• Preferred: Background in Xilinx IP and SoCs, AXI, PCIe, SpaceWire, Ethernet, DSP, hardware debug, or GitLab CI.