
Verification Engineer
Posted Oct 16

Posted Oct 16
This is a fully remote position, open to applicants in United States.
• Design, implement, and sustain RTL verification environments utilizing UVM or comparable methodologies.
• Formulate and execute coverage-driven verification strategies that align with design specifications.
• Create directed and constrained-random test cases and sequences to validate functionality and pinpoint edge cases.
• Examine simulation outcomes, troubleshoot intricate verification and design challenges, and conduct root-cause analysis in collaboration with RTL design engineers.
• Implement and monitor functional and code coverage, steering verification towards completion.
• Develop reusable verification components and author SystemVerilog Assertions (SVA).
• Engage in design and verification reviews, offering insights on design testability, accuracy, and optimization.
• Automate regression testing and improve verification infrastructure through Python and scripting.
• Contribute to the ongoing enhancement of verification processes, tools, and methodologies.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Over 7 years of experience in digital design verification.
• Extensive hands-on experience with UVM-based or similar verification methodologies.
• Proficient in SystemVerilog, UVM, and Python.
• Familiarity with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium).
• Strong understanding of digital design principles.
• Experience in verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB.
• Knowledge of high-speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C.
• Excellent analytical and problem-solving capabilities.
• Strong written and verbal communication skills for effective cross-functional collaboration.
• Keen attention to detail and the ability to produce reliable, high-quality verification results.
• Capability to work independently and oversee tasks to completion.
• Familiarity with formal verification techniques and tools.
• Experience in verifying processor subsystems or SoC-level designs.
• Authorization to work in the United States is addressed in the application form.
• Visa sponsorship requirements for work in the United States are addressed in the application form.
• Meaningful equity.
• Comprehensive benefits package.
• 401(k) plan.
Sargent & Lundy
Willow Innovations, Inc.
Astrolab
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