Synthesis or Formal Verification Developer

This is a fully remote position, open to applicants anywhere in the world.

📋 Description

• Contribute to YosysHQ’s areas of focus in synthesis or formal verification.

• Develop and maintain open-source EDA tools and software packages.

• Engage in formal verification tools using C++, Rust, and Python.

• Implement hardware model checking and associated formal methods.

• Develop synthesis capabilities leveraging C++ and RTL hardware design expertise.

• Work on bespoke development of specific features and complete workflows based on YosysHQ software components.

• Provide support and training for users and developers utilizing the software.

• Take independent ownership of assigned tasks and tackle challenges effectively.

• Attend team meetings typically scheduled between 3pm and 6pm Vienna time (CET/CEST).

⛳️ Requirements

• Proficient in C++ or Rust for formal verification; open to learning the other languages and Python.

• Familiar with hardware model checking implementations, or possess a background in verification/formal methods such as SAT/SMT solving, automated/interactive theorem proving, programming language theory, or automata theory.

• Some exposure to RTL hardware design relevant to formal verification.

• Proficient in C++ for synthesis tasks.

• Some experience with RTL hardware design, preferably for ASIC projects.

• Relevant experience in building software for engineering or scientific applications, implementing algorithms from academic literature, or working on a compiler.

• Experience in adapting to a large, pre-existing project.

• Capable of taking initiative, working autonomously, and addressing challenges with minimal supervision.

• Must not reside in a country subject to sanctions or export restrictions, nor be prohibited from performing work for the US government.

• A CV and a brief cover letter are mandatory for application.

🏝️ Benefits

• Flexible remote work from any location.

• Flexible work schedule; choose your hours outside of team meetings.

• Part-time option available for 1–5 days per week.

• Flat pay structure with uniform rates for all employees.

• Opportunity to contribute to open-source EDA projects.

• Engage with synthesis and formal verification technologies.

• Receive support and training for users and developers of the software packages.