Senior NoC Research Engineer – Network-on-Chip

This is a fully remote position, open to applicants in Germany.

📋 Description

• Investigate and assess NoC topologies, router and switch configurations, arbitration mechanisms, flow control, QoS, and congestion management.

• Create and uphold architectural models and simulations utilizing SST, gem5, or custom cycle-level and analytical frameworks.

• Develop traffic generators that accurately represent real ML workloads, encompassing collective communication, tensor parallelism, and memory traffic.

• Analyze power, performance, and area (PPA) trade-offs, substantiating recommendations with quantitative data.

• Guarantee designs are free from deadlock and livelock through analysis, formal methods, or simulation techniques.

• Explore adaptive routing strategies and various topology alternatives.

• Convert intricate protocol and IP specifications, such as AXI, CHI, and APB, into concise design requirements.

• Evaluate third-party interconnect IP and assist in making build-versus-buy decisions.

• Examine RDMA concepts and chip-to-chip interfaces for efficient data movement between accelerators at the system level.

• Share insights and recommendations with architecture and leadership teams.

• Contribute to publications and patents related to on-chip networks and data movement for ML.

• Report directly to the CTO and collaborate with teams focused on chip architecture, hardware, and software.

⛳️ Requirements

• PhD or a Master's degree with equivalent research experience in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.

• Proven senior-level experience in NoC or interconnect architecture, either in an industrial setting or applied research.

• Strong expertise in on-chip interconnect and traffic management, including NoC topologies, routers, switches, arbitration, flow control, QoS, and congestion control.

• Solid understanding of ML workloads and accelerator architectures, with a focus on collective communication, tensor parallelism, and memory traffic.

• Familiarity with on-chip protocols like AXI, CHI, or AHB.

• Comprehension of RDMA concepts and transport mechanisms (InfiniBand, RoCE), including queue pairs, memory registration, and zero-copy transfers.

• Experience in evaluating PPA trade-offs using quantitative evidence.

• Proficiency in architectural modeling and simulation (SST, gem5, or custom models), along with strong skills in Python and C++.

• Capability to interpret complex protocol and IP specifications and translate them into precise design requirements.

• Experience in avoiding deadlock and livelock, as well as exploring adaptive routing or topology options.

• Excellent written and verbal communication skills in English, complemented by a proactive, collaborative approach to solving open-ended challenges.

🏝️ Benefits

• 30 days of annual vacation.

• Up to 2 weeks of work abroad.

• Opportunity to work on state-of-the-art sparse computing technology.

• High-impact position with a direct effect on the architecture of SpiNNext.

• Collaborative team environment with seasoned engineers from both academia and industry.

• Equity participation in a burgeoning deep-tech company.