
Senior DFT Engineer
Posted Oct 12

Posted Oct 12
This is a fully remote position, open to applicants in Poland.
• Take ownership of Design-for-Test (DFT) for customer System-on-Chips (SoCs) from start to finish.
• Define and execute the DFT architecture.
• Manage scan and Automatic Test Pattern Generation (ATPG), including the generation and validation of patterns.
• Implement memory Built-In Self-Test (BIST) and boundary scan techniques.
• Conduct pattern validation via gate-level simulations.
• Perform DFT Design Rule Check (DRC) analysis and troubleshoot test coverage.
• Enhance test coverage across necessary fault models.
• Oversee the entire DFT process from concept to tape-out and facilitate production test hand-off.
• Automate processes using Perl, Tcl, UNIX scripting, and possibly Python.
• Assist in the production test hand-off.
• Bachelor of Science in Electrical Engineering from an accredited institution.
• At least 3 years of practical DFT experience is essential; senior profiles are preferred.
• Familiarity with scan, ATPG, at-speed testing, memory BIST, and I/O DFT methodologies.
• Experience with scan insertion and ATPG for stuck-at, transition-delay, bridging, and IDDQ fault models.
• Proven track record of improving test coverage.
• Experience conducting DFT DRC analysis and debugging coverage using Synopsys DFT Compiler, TestMAX (TetraMAX), SpyGlass DFT, or similar Siemens (Mentor) Tessent tools.
• Proficient with Tessent MBIST.
• Solid understanding of JTAG IEEE 1149.1, IEEE 1149.6, and IEEE 1500 (formerly P1500).
• Hands-on experience in designing and implementing DFT features.
• Ownership of the complete DFT flow from conceptualization to tape-out and production.
• Experience in setting up and executing gate-level simulations for pattern validation.
• Familiarity with formal equivalence checking.
• Proficient in Perl, Tcl, and UNIX scripting for automating flows.
• Nice to have: broader experience with Siemens Tessent tools, including ScanPro, TestKompress, and LBIST.
• Nice to have: advanced-node experience at 7nm and smaller.
• Nice to have: Python experience for flow automation.
• Competitive salary and performance-based bonuses.
• Comprehensive health, dental, and vision insurance.
• Retirement savings plan with company match.
• Opportunities for professional development and training.
• Flexible work hours and remote work options.
Sargent & Lundy
Willow Innovations, Inc.
Astrolab
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