This is a fully remote position, open to applicants in India.

• Take ownership of verification planning and execution for designated IP blocks and features at both IP and subsystem levels.

• Develop scalable verification environments utilizing reusable testbenches, checkers, constrained-random tests, and debugging infrastructure.

• Collaborate effectively with architecture, design, and software teams.

• Analyze simulation failures, quickly identify root causes, and ensure issues are resolved.

• Lead functional coverage planning and achieve coverage closure for assigned blocks.

• Contribute to both simulation and formal verification initiatives.

• Begin mentoring junior engineers.

• BS/MS in Electrical Engineering, Computer Science, or a related discipline.

• 8-12 years of pertinent experience in design verification.

• Strong knowledge of interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe.

• Solid foundation in simulation-based verification methodologies, including UVM, SVA, and ABV.

• Hands-on coding skills in System Verilog/UVM, C/C++, and Python.

• Comfortable using AI-assisted development tools.

• Flexible work arrangements.

• Professional development opportunities.

Senior Design Verification Engineer

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