Lead STA Engineer

This is a fully remote position, open to applicants in California, +2 more states.

📋 Description

• Lead the development of timing flows and methodologies for cutting-edge FinFET and multi-patterning technologies from the ground up using Cadence Tempus or Synopsys PrimeTime.

• Take ownership of timing convergence for IP, subsystem, and SoC blocks.

• Establish timing margining, PVTRC corner definitions, extraction methodologies, and signoff timing to ensure correlation with synthesis/place-and-route.

• Create slew-rate and glitch-noise checks to guarantee high design quality.

• Formulate custom timing checks tailored for Efficient's proprietary ultra-low-power architecture.

• Collaborate closely with RTL, DFT, and IP vendor teams to define and enforce SDC constraints.

• Comprehend all collateral associated with both hard and soft IP utilized in the design.

• Work in partnership with post-silicon product bring-up teams to achieve timing correlation from pre-silicon to post-silicon.

• Coordinate with third-party vendor resources to manage timing-domain tasks.

• Strive for continuous improvement in flow consistency and efficiency across various product-type swim lanes.

⛳️ Requirements

• Master's degree in Electrical Engineering with over 5 years of industry experience or a PhD in Electrical Engineering with more than 3 years of industry experience.

• Demonstrated success in delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in process technologies at 12nm or smaller.

• Familiarity with EDA flow utilizing Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) employing hierarchical design and abstraction techniques.

• Practical experience in timing convergence for high-frequency and low-power designs.

• In-depth knowledge of static timing analysis, including defining constraints and exceptions, corners/voltage definitions, and timing margining.

• Experience with low power implementation commonly seen in the industry and understanding how timing convergence influences power consumption, ensuring optimal trade-offs.

• Strong scripting abilities in TCL, shell, and Python.

• Understanding of computer architecture.

• Familiarity with physical design and ASIC implementation.

• Experience in full chip sign-off budgeting.

• Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology, along with their implications for physical design.

• Proficient in industry-standard physical design flow and capable of building CAD flow infrastructure for PD engineers.

• Ability to define design constraints for static timing analysis and corners/voltage definitions.

• Experience integrating analog or mixed-signal macros into top-level designs.

🏝️ Benefits

• 10% annual bonus.

• Meaningful equity.

• 401K match.

• Company-paid benefits.

• Paid parental leave.

• Flexibility.

• Opportunities for personal and professional development.