Lead Analog Layout Engineer

This is a fully remote position, open to applicants in Canada.

📋 Description

• Take ownership of designated layout projects, managing them from feasibility and floorplanning to implementation, physical verification, integration, and readiness for tapeout.

• Outline project scope, develop implementation strategies, estimate effort, establish milestones, and set up review checkpoints.

• Coordinate with contributors, monitor dependencies, and address any implementation challenges.

• Facilitate layout reviews and quality assessments alongside layout teams and circuit designers.

• Define implementation constraints while assessing performance, area, device matching, parasitics, isolation, and reliability trade-offs.

• Create layout strategies for circuits that are performance-sensitive and for high-speed signal pathways.

• Examine extracted parasitics and implement focused enhancements.

• Lead the closure of physical verification and reliability, covering DRC, LVS, ERC, antenna, BUMP, EM/IR, and PERC checks.

• Guide junior engineers through practical problem-solving and design critiques.

• Collaborate with CAD and AI/ML engineers on setting up environments, evaluating tools, automating processes, creating reusable layout structures, generating RFIC and analog layouts, developing PCells, and exploring design spaces.

• Share updates on progress, risks, and necessary corrective actions related to milestones.

⛳️ Requirements

• A Bachelor’s degree or higher in Electrical Engineering, or a related discipline.

• Over 5 years of experience in custom analog or mixed-signal IC layout.

• Proven track record of managing complex layouts through successful tapeouts.

• Experience in making independent technical decisions and delivering projects.

• Background in guiding layout contributors and executing hands-on implementations.

• Familiarity with ADCs, DACs, SerDes, PLLs, high-speed amplifiers, or precision analog circuits.

• Expertise in Cadence Virtuoso and Siemens Calibre, or similar custom-layout and physical-verification tools.

• Understanding of device matching, parasitic resistance and capacitance, coupling, high-frequency routing, shielding, ESD-aware layout, electromigration, and IR drop.

• Knowledge of deep-submicron CMOS processes, foundry design rules, device isolation, and layout-dependent phenomena.

• Hands-on experience with FinFET layout and advanced-node implementations.

• Experience in high-speed SerDes or data converters.

• Familiarity with Ansys Totem or similar EM/IR tools and PERC-based ESD and reliability troubleshooting.

• Comprehensive understanding of noise isolation and shielding techniques.

• Skills in PCell development and layout automation.

• Experience utilizing AI-assisted coding tools for layout-flow scripting, automation, and engineering utilities.

🏝️ Benefits

• Opportunities for professional development.

• Flexible work arrangements.

• Medical, dental, and vision insurance plans.

• DCPP (Canada) with company matching.

• Employee Stock Purchase Program (ESPP).

• Employee Assistance Program (EAP).

• Paid holidays provided by the company.

• Paid sick leave.

• Vacation time.

• Paid Family Leave and additional leave options.