DFT Engineer

atDelos DataRemoteUS flagUnited StatesFull-timeEngineerMid-levelSenior$160k – $230k/year

Posted 3 days ago

This is a fully remote position, open to applicants in United States.

📋 Description

• Design, implement, and sustain RTL verification environments utilizing UVM or similar methodologies.

• Develop and execute coverage-driven verification strategies that align with design specifications.

• Employ EDA DFT tools like TestMax and Tessent to generate and execute pre-silicon test cases for MBIST and scan fabric.

• Create directed test cases for DFT logic not provided by vendors.

• Aid in the verification of ATPG patterns, particularly at the SoC level, along with manufacturing reset sequences.

• Examine simulation results, troubleshoot intricate verification and design challenges, and conduct root-cause analysis alongside DFT design engineers.

• Implement and monitor functional and code coverage, steering verification processes towards closure.

• Create reusable verification components and draft SystemVerilog Assertions.

• Engage in design and verification reviews, enhancing testability, accuracy, and optimization.

• Automate regression testing and improve verification infrastructure through Python and scripting.

• Contribute to the ongoing enhancement of verification processes, tools, and methodologies.

• Assist with post-silicon test bring-up debugging alongside DFT designers.


⛳️ Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.

• Over 5 years of experience in digital design verification, including at least 2 years in DFT verification specifically.

• Robust hands-on experience with UVM-based or comparable verification methodologies.

• Proficient in SystemVerilog.

• Familiarity with scripting, preferably using Python, and automation techniques.

• Experienced with Synopsys VCS, Siemens/Mentor Questa, or Cadence Xcelium.

• Knowledgeable in Synopsys TestMax + Yield Accelerator or Siemens Tessent.

• Strong grasp of digital design principles.

• Experience validating test sequences for high-speed PHY logic, including PCIe and Ethernet (10G/40G/100G).

• Excellent analytical and problem-solving capabilities.

• Effective written and verbal communication skills for collaborative efforts across functions.

• Keen attention to detail and capacity to deliver dependable, high-quality verification results.

• Capability to work autonomously and manage tasks to completion.

• Familiar with change control systems, particularly git.

• Experience in verifying SoC-level designs.


🏝️ Benefits

• Meaningful equity.

• Comprehensive benefits package.

• 401(k) plan.

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