Design Verification Engineer

This is a fully remote position, open to applicants in Romania.

📋 Description

• Create and sustain SystemVerilog/UVM verification environments for SerDes and PHY components.

• Develop testbenches, functional coverage models, and assertions.

• Execute simulations, evaluate failures, and troubleshoot both RTL and testbench challenges.

• Work collaboratively with design, architecture, and analog teams on verification at both block-level and top-level.

⛳️ Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.

• 0–5 years of experience in digital design or verification, which can include internships, academic projects, or relevant industry experience.

• Proficient understanding of SystemVerilog and a basic grasp of UVM concepts.

• Strong foundation in digital design principles: synchronous logic, FSMs, pipelining, and clock domain crossing.

• Excellent analytical and debugging skills — you thrive on uncovering solutions to problems.

• Effective communication skills in English, both spoken and written.

🏝️ Benefits

• Health insurance.

• Opportunities for professional development.