Analog Layout Engineer

This is a fully remote position, open to applicants in Texas.

📋 Description

• Develop physical silicon layouts for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and other high-speed components.

• Generate both block-level and chip-top-level floor plans.

• Oversee the integration of hierarchical blocks.

• Manage co-design processes that consider micro-bump or package awareness.

• Tackle layout-dependent effects, ensuring device matching, implementing common-centroid structures, and integrating guard rings and isolation or shielding techniques.

• Achieve closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection requirements.

⛳️ Requirements

• A minimum of 7 years of relevant industry experience.

• Typically 5 to 12+ years of direct custom IC layout experience within deep sub-micron or advanced CMOS/FinFET nodes.

• Critical experience at lower nodes (N3, N5).

• Mandatory experience with TSMC 4NM technology.

• Proficiency in high-speed analog layout techniques.

• Familiarity with floor planning and integration processes, encompassing block-level and chip-top-level floor plans, hierarchical block integration, and micro-bump or package-aware co-design.

• Understanding of layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and methods for isolation or shielding.

• Competence in DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection methodologies.

• Must be eligible to work under the specified visa requirements; H1B transfers are not permitted.

🏝️ Benefits

• Contract employment opportunities.

• Acceptance of all visa types, except for H1B transfers.

• C2C engagements are permitted.