Analog Layout Engineer

This is a fully remote position, open to applicants in Texas.

📋 Description

• Develop physical silicon layouts for high-frequency or high-speed mixed-signal circuits

• Construct block-level and chip-top-level floor plans

• Oversee hierarchical block integration

• Manage micro-bump or package-aware co-design

• Mitigate layout-dependent effects, device matching, common-centroid structures, guard rings, and isolation or shielding

• Achieve compliance with DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection

⛳️ Requirements

• Minimum of 7 years of relevant experience required

• Typically 5 to 12+ years of practical custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes

• Critical experience at lower nodes (N3, N5)

• TSMC 4NM experience is essential

• Proficient in high-speed analog layout for mixed-signal circuits such as SerDes, ADCs, DACs, PLLs, and high-speed blocks

• Familiarity with block-level and chip-top-level floor planning

• Experience in managing hierarchical block integration

• Background in micro-bump or package-aware co-design

• Understanding of layout-dependent effects (LOD, WPE, LDE)

• Knowledge of device matching and common-centroid structures

• Experience with guard rings and isolation or shielding, including coaxial, differential, and ground shields

• Proven track record of ensuring compliance with DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection

• Must possess authorization to work under an eligible visa status; H1B transfers are not allowed

🏝️ Benefits

• Option for remote work

• Contract-based engagement

• Acceptance of all visa types except H1B transfers

• C2C engagements permitted