Senior LPU ASIC Engineer

This is a fully remote position, open to applicants in Arizona, +3 more states.

📋 Description

• Accountable for Synthesis, floorplanning, place & route, timing constraints, UPF, and LEC.

• Collaborate with IP, Front-End logic design, and Architecture teams for optimization purposes.

• Spearhead design closure to ensure 100% verification compliance for GDSII handoff and tapeout.

• Design architect data-driven EDA flows and methodologies with automated enhancements.

⛳️ Requirements

• Bachelor’s degree in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred).

• Over 5 years of industry experience in delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes.

• Demonstrated success in guiding designs through the complete RTL-to-GDSII flow.

• In-depth knowledge of low-power design intent (UPF/CPF).

• Advanced proficiency in clock tree synthesis methodologies, CTS, and sign-off timing analysis (MCMM STA).

• Strong expertise in power grid design, EMIR analysis, and ECO generation.

• Competent in applying best-known methods to enhance DFT structures.

• Mastery of industry-standard tool suites for complete physical design flows.

• Skilled in scripting languages such as TCL, Python, and Perl.

🏝️ Benefits

• Comprehensive benefits package.

• Health insurance.

• Retirement plans.

• Paid time off.

• Flexible work arrangements.

• Professional development opportunities.

• Equity options.