Senior ASIC Verification Engineer

This is a fully remote position, open to applicants in California.

📋 Description

• Engage in the comprehensive development of UVM environments to validate RTL at block, unit, and SoC levels.

• Design and implement functional tests in accordance with verification test plans.

• Enhance the testbench for functional and code coverage, driving closure based on coverage metrics.

• Work collaboratively with cross-functional teams, including design, software, emulation, and silicon validation, to ensure the highest quality in design.

⛳️ Requirements

• Over 10 years of experience in coding with System Verilog Language.

• Proven experience in verifying complex SoCs that encompass multiple clock and reset domains, utilizing VCS or similar simulation tools.

• Proficient in debugging failures down to the RTL level and resolving bug fixes using Verdi or comparable debugging tools.

• Background in developing testbenches from the ground up.

• Familiarity with version control systems such as Git or SVN.

• Bachelor’s Degree in Computer Engineering, Computer Science, or Electrical Engineering.

🏝️ Benefits

• Health insurance.

• 401(k) with company matching.

• Generous paid holidays.

• Open Time Off (OTO).

• Disability and life insurance.

• Accidental injury insurance.

• Pet insurance.

• Medical, dental, and vision coverage.