Senior ASIC Verification Engineer

This is a fully remote position, open to applicants in California.

📋 Description

• Accountable for the verification closure of design modules or subsystems from test planning through to verification completion.

• Engage in the foundational development of UVM environments to validate RTL at the block, unit, and SoC levels.

• Create and implement functional tests in accordance with verification test plans.

• Equip the testbench for functional and code coverage, driving to closure based on coverage metrics.

• Work collaboratively with cross-functional teams, including design, software, emulation, and silicon validation teams, to guarantee the highest design quality.

⛳️ Requirements

• Over 10 years of experience in networking hardware verification.

• Proficient in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, as well as UDP, TCP/IP, RDMA/RoCE, and IPSec.

• Skilled in System Verilog Language.

• Experience with VCS or similar simulation tools.

• Expertise in ground-up testbench development and debugging using Verdi or comparable tools.

• Knowledge of Git or SVN.

• Bachelor’s Degree in Computer Engineering, Computer Science, or Electrical Engineering.

• Master’s Degree in Computer Engineering, Computer Science, or Electrical Engineering (preferred).

🏝️ Benefits

• Competitive compensation package that includes equity, cash, and incentives.

• Health insurance coverage encompassing medical, dental, and vision.

• Retirement benefits featuring a 401(k) plan with company matching.

• Paid holidays.

• Open Time Off (OTO) policy for regular full-time exempt employees.

• Sick leave, bonding leave, and pregnancy disability leave.