Physical Design

This is a fully remote position, open to applicants in India.

📋 Description

• Execute the entire Physical Design workflow from Netlist to GDSII.

• Conduct floorplanning, power planning, placement, clock tree synthesis, routing, and physical verification.

• Lead timing closure while achieving performance, power, and area objectives.

• Carry out congestion analysis and enhance placement and routing.

• Evaluate and rectify setup/hold timing violations across all design corners and modes.

• Conduct physical signoff including DRC, LVS, IR Drop, EM, and antenna checks.

• Collaborate with RTL, DFT, STA, and Packaging teams to ensure successful tape-out.

• Troubleshoot and resolve implementation challenges while maintaining design quality.

• Assist in ECO implementation and timing closure tasks.

• Ensure successful tape-out on advanced technology nodes.

⛳️ Requirements

• Over 6 years of hands-on experience in ASIC/SoC Physical Design.

• Extensive experience in the complete RTL-to-GDSII implementation process.

• Proficiency in floorplanning, power planning, placement and optimization, CTS, routing, physical verification, and ECO implementation.

• Strong experience in timing closure with setup and hold optimization.

• Practical experience with Cadence Innovus.

• Familiarity with Synopsys ICC2 is a plus.

• Solid understanding of Static Timing Analysis (STA) principles.

• Experience with IR Drop, EM Analysis, Crosstalk, Noise, and Signal Integrity.

• Hands-on experience with Calibre for DRC/LVS signoff.

• Experience with advanced technology nodes including 2nm, 3nm, 5nm, 7nm, 12nm, 16nm, and FinFET.

• Good grasp of low-power implementation techniques using UPF/CPF.

• Experience in block-level or chip-level tape-out.

• Strong debugging and problem-solving abilities.

• Familiarity with Fusion Compiler implementation flow is an asset.

• Practical experience with Synopsys PrimeTime and PrimeTime-SI is a bonus.

• Experience using RedHawk or Voltus for Power Integrity analysis is advantageous.

• Knowledge of Formality and logical equivalence checking is beneficial.

• Experience with hierarchical SoC implementation is a plus.

• Scripting skills in TCL, Python, or Perl are desirable.

• Exposure to multi-voltage and multi-power domain designs is favorable.

• Experience with CPU, GPU, AI/ML, Networking, Mobile, Automotive, or HPC SoCs is advantageous.

• Familiarity with advanced packaging technologies such as 2.5D/3D ICs is a plus.

• Prior experience in customer-facing roles or offshore/on-site collaboration is a plus.

• A Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field is preferred but not mandatory.

• Ability to work both independently and collaboratively in a dynamic semiconductor development environment.

🏝️ Benefits

• Competitive salary and performance-based bonuses.

• Comprehensive health, dental, and vision insurance.

• Opportunities for professional development and continuing education.

• Flexible work hours and a supportive work-life balance.

• Engaging work environment with innovative projects.